1. Field of the Invention
The present invention relates to the stabilization of a differential amplifier circuit that is insensitive to variations in supply voltage and transconductance.
2. Art Background
High performance integrated circuits often transmit and receive data differentially: two wires (e.g., data and dataB) sent one binary digit (bit). If the voltage on wire data is larger than the voltage on wire dataB, then the bit is a value of one. If the voltage on dataB is larger than the voltage on data, then the bit is a value of zero. This is called "differential signaling" because the voltage difference encodes the bit: one if the difference is positive, zero if the difference is negative.
Differential signaling can operate at very high speeds, because it allows the integrated circuit designer to use small voltage swings and yet retain good noise rejection. To operate at a high speed, the circuit delay (.DELTA.t) must be minimized. Delay is a function of the current (I) used to drive the signal wire, the capacitance (C) on the wire, and the voltage swing (.DELTA.V) selected by the integrated circuit designer: ##EQU1##
As can be seen, high speed (small .DELTA.t) may be achieved by reducing the capacitance C, increasing the current I, or reducing the voltage swing .DELTA.V. Unfortunately, it is usually impossible to reduce C; wires must travel long distances, transistor sizes cannot be decreased, etc. Similarly, it is often impractical or impossible to increase the driving current I, because that would raise power consumption to unacceptable levels. Therefore, integrated circuit designers usually must reduce delay be reducing voltage swing (.DELTA.V).
Reduced voltage swing can become problematic, though, because it also reduces noise rejection. The smaller the swing, the easier for noise to disturb or overpower the intended data signal. Differential signaling offers a substantial improvement as the noise is often equally coupled into both wires of a differential signal-pair and the voltage difference between the wires is therefore unaffected. This type of disturbance, called common-mode noise, is completely rejected by differential signaling. Because of its superior common-mode noise rejection, differential signaling can operate at much smaller voltage swing .DELTA.V than nondifferential ("single ended") signaling.
However, integrated circuits encounter additional types of imbalances besides common-mode noise. Manufacturing tolerances cause pairs of elements, designed and intended to be "identical", to have slight mismatches. (The worse the tolerances, the worse the mismatch.) Mismatches can cause "differential driver" circuits and "differential receiver" circuits to favor one data state over the other, a condition know as offset. Additionally, noise can couple into one wire of a differential signal-pair more than it couples into the other wire; this is called differential-mode noise. Each of these mechanisms serves to disturb the data being sent on the differential pair, forcing the designer to use a larger voltage swing .DELTA.V to be certain of reliable data transmission.
Thus, integrated circuit designers strive to balance conflicting requirements; use as small a voltage swing .DELTA.V as possible (for small delay), but not too small (otherwise the data can be corrupted by mismatches and differential-mode noise).
Another factor which complicates the design process is that the voltage swing .DELTA.V usually varies with supply voltage and field effect transistor "strength" (transconductance). Thus the designer must arrange the circuit so that under all possible conditions, the voltage swing .DELTA.V never falls below the required minimum. The designer therefore adjusts the circuit so that under the worst-case conditions (which cause the smallest swing .DELTA.V), .DELTA.V is still adequately large. The typical swing .DELTA.V, with nominal values of supply voltage and transistor strength, is larger than necessary. The larger swing means the circuit delay is bigger than it otherwise might be.
FIG. 1 shows a prior art differential amplifier and bias circuit. PMOS load transistors M1, M2 operate in the triode or "linear" region; the gates connect to VSS. The bias circuit consists of devices M6 and M7. These bias devices produce the gate voltage for the current source transistor M5 of the differential amplifier. The output voltage swing is given by .DELTA.V=IR, where I is the current source value (M5's drain current), and R is the effective resistance of the triode-load PMOS transistor (M1 and M2).
The output swing .DELTA.V from this prior art circuit is not stabilized against variations in the supply voltage VDD. If VDD increases, the gate-to-source voltage of the PMOS loads M1 and M2 increases. Since M1 and M2 are in the linear region, the effective resistance R decreases linearly with VDD. However, the bias current through M6 and M7 increases super-linearly with VDD; in classical theory this current increases as the square of VDD since both M6 and M7 are saturated. (Modern short-channel devices, specifically PMOS transistors like M6, have currents that increase as approximately VDD to the power 1.4.) In any case, the super-linear increase in bias current I and the linear decrease in load resistance R, provides that the voltage swing .DELTA.V=IR increases when VDD increases. Similarly, .DELTA.V decreases when VDD decreases.
The output swing .DELTA.V from this prior art circuit is also not stabilized against variations in device transconductance. Transconductance variations can arise in manufacturing, from variations in the line width of the transistor gate electrode, from differences in the gate oxide thickness, or from differences in the source/drain "underdiffusion" beneath the gate. If the transconductance of the NMOS transistors increases, while that of the PMOS transistors is unaffected, the current in bias stage M6, M7 increases and therefore current source transistor M5 sinks more current I. However, load transistors M1 and M2 are unaffected, so the resistance R remains unchanged. Therefore the voltage swing .DELTA.V=IR increases. Similarly, .DELTA.V decreases when NMOS transconductance increases.